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4.5.2
SPI Data Output Verification Error
The device includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted
on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch
Fault is detected and the MISOERR flag in the DEVSTAT register is set.
If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI accel-
eration request message is ignored and the device responds with a “MISO Error” response during the subsequent SPI message
(reference Table 30 ). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by
the MISO mismatch failure.
If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register
write is completed as requested, but the device responds with a “MISO Error” response as shown in Table 30 , during the subse-
quent SPI message.
If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register
read is ignored and the device responds with a “MISO Error” response as shown in Table 30 , during the subsequent SPI mes-
sage. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared.
In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the
DEVSTAT register is completed.
SPI DATA OUT SHIFT REGISTER
DATA OUT BUFFER
D
Q
D
Q
MISO
R
SCLK
4.5.3
Invalid Requests
Figure 37. SPI Data Output Verification
D
R
Q
MISO ERR
4.5.3.1 Acceleration Data Request Mismatch Failure
The device detects an “Acceleration Data Request Mismatch” error if the SPI “Acceleration Data Request” Command data
listed in Table 32 does not match the internal register settings. The device responds to an “Acceleration Data Request Mismatch”
error with an “Invalid Accel Request” response as specified in Table 30 on the subsequent SPI message only. No internal fault is
recorded. The arming function will not be updated if an “Acceleration Data Request Mismatch” Error is detected. The PCM output
is not affected by the “Acceleration Data Request Mismatch” error.
Register operations will be executed as specified in Section 4.4 .
4.5.3.2 Invalid Register Request
The following conditions result in an “Invalid Register Request” error:
? An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1 , Table 3 ). Attempts to
write to registers $09, $18, $19, $1A and $1B will result in an error.
? An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set
– This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
?
An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1 , Table 3 ). Attempts to
read registers $09, $18, $19, $1A and $1B will result in an error.
The device responds to an Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30 .
4.5.4
Device Reset Indications
If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.11 , the device will respond to ac-
celeration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT
bit is cleared automatically when device initialization is complete (Reference t OP in Section 2.7 ). The DEVRES bit is cleared on
a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT
or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.
MMA65xx
Sensor
Freescale Semiconductor, Inc.
51
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